Gate patterning is obtained by etching polysilicon on silicon oxide, or the gate oxide. With the continued scaling of the gate oxide into the sub-20 xc3x85 regime with sub-0.1 xcexcm technology, it is becoming increasingly difficult to ensure that the gate polysilicon etch does not also etch through the gate oxide and damaging the underlying substrate.
U.S. Pat. No. 5,924,001 to Yang et al. describes a method for fabricating polycide gate electrodes wherein voids at the silicide/polysilicon interface are eliminated by ion implantation. A hard mask layer is deposited over the silicide layer that overlies the polysilicon gate conductor.
U.S. Pat. No. 5,897,366 to Shiralagi et al. describes a method of resistless gate metal etch in the formation of a field effect transistor.
U.S. Pat. No. 5,705,414 to Lustig describes a method of fabricating a gate electrode for a MOS (metal oxide semiconductor) transistor using a spacer/hardmask gate patterning process.
U.S. Pat. No. 5,438,006 to Chang et al. describes a process of fabricating an integrated circuit device having a reduced-height gate stack by using a patterned oxide hard mask to pattern the underlying metal layer. The oxide hard mask is removed and the patterned metal is used as a mask to etch the polysilicon layer.
xe2x80x9cSub-5 nm Multiple-Thickness Gate Oxide Technology Using Oxygen Implantation,xe2x80x9d Y. C. King, C. Kuo, T. J. King, and C. Hu; IEDM Tech. Dig., p. 21-1, 1998 describes a process of a moderate oxygen implantation followed by a moderate anneal within a polysilicon layer to form a layer of high-quality oxide having a thickness from 30-50 xc3x85 within the polysilicon layer.
Accordingly, it is an object of the present invention to provide a method of gate patterning for sub-20 xc3x85 gate oxide regime.
Another object of the present invention is to provide a method of forming a gate oxide without etching through the gate oxide and damaging the underlying substrate when etching the polysilicon layer to form the polysilicon gate conductor.
Yet another object of the present invention is to provide a smaller rule polysilicon-on-oxide etch method without requiring a new etch chemistry or additional mask sets.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor structure having an upper silicon layer is provided. The semiconductor structure has a gate conductor region. A first gate oxide layer is formed over the semiconductor structure. A polysilicon layer is formed over the first gate oxide layer. A patterned oxide mask and photoresist layer are formed over the polysilicon layer within the gate conductor region leaving unmasked polysilicon layer portions and unmasked first gate oxide layer portions. An oxygen implant is conducted within the unmasked polysilicon layer portions proximate the unmasked first gate oxide layer portions. The patterned photoresist mask is removed. The structure is annealed to form second gate oxide portions within the unmasked polysilicon layer portions over the unmasked first gate oxide layer portions. The unmasked polysilicon layer portions are etched and removed to the second gate oxide portions forming a polysilicon gate conductor within the gate conductor region.